The invention relates to a video signal processing circuit including a clock signal generating circuit which comprises a phase detector having a first input for a line synchronizing signal, a second input which is coupled to an output of a clock signal generator at least via a frequency divider and a control signal output which is coupled to a control signal input of the clock signal generator.
A video signal processing circuit of the type described above is known from European Patent Specification 70465 and it comprises a memory circuit which is used to increase the field frequency of the video signal. The memory circuit is written and read by means of clock signals which are derived from a clock signal generated by a single clock signal generator. If such a video signal processing circuit must be used for processing video signals from a video recorder, it is found to be difficult to obtain a satisfactory filtering of the output signal of the phase detector by using conventional loop filter circuits.
It is an object of the invention to provide a solution to this problem.